HD6417705F133V Datasheet, PDF (248/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

This LSI
A14
A13
A12
A1
CKIO
CKE
CSn
RASx
CASx
RD/WR
D15
D0
DQMLU
DQMLL
64M synchronous DRAM
(1M × 16-bit × 4-bank)
A13
A12
A11
A0
CLK
CKE
CS
RAS
CAS
WE
DQ15
DQ0
DQMU
DQML
Note: x is U or L
Figure 7.15 Example of 64-MBit Synchronous DRAM (16-Bit Data Bus)
7.8.2 Address Multiplexing
An address multiplexing is specified so that SDRAM can be connected without external
multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, AxROW[1:0] and
AxCOL[1:0] in SDCR. Tables 7.10 to 7.15 show the relationship between the settings of bits
BSZ[1:0], AxROW[1:0], and AxCOL[1:0] and the bits output at the address pins. Do not specify
those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed.
A25 to A18 are not multiplexed and the original values of address are always output at these pins.
When the data bus width is 16 bits (BSZ[1:0] = 10), A0 of SDRAM specifies a word address.
Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the
A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ[1:0] = 11), the A0 pin of
SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of
the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on.
Rev. 2.00, 09/03, page 200 of 690