HD6417705F133V Datasheet, PDF (173/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
6.1 Features
• 16 levels of interrupt priority can be set
By setting the interrupt priority registers, the priorities of on-chip peripheral modules, and IRQ
interrupts can be selected from 16 levels for individual request sources.
• NMI noise canceller function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as a noise
canceller.
• IRQ interrupts can be set
Detection of low level, high level, rising edge, or falling edge
Rev. 2.00, 09/03, page 125 of 690