HD6417705F133V Datasheet, PDF (45/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Bus State Controller (BSC)
Table 7.1 Pin Configuration ................................................................................................. 151
Table 7.2 Physical Address Space Map ................................................................................ 152
Table 7.3 Correspondence between External Pins (MD3 and MD4) and Memory Size .......... 154
Table 7.4 32-Bit External Device/Big Endian Access and Data Alignment............................ 181
Table 7.5 16-Bit External Device/Big Endian Access and Data Alignment............................ 182
Table 7.6 8-Bit External Device/Big Endian Access and Data Alignment ............................. 183
Table 7.7 32-Bit External Device/Little Endian Access and Data Alignment......................... 184
Table 7.8 16-Bit External Device/Little Endian Access and Data Alignment......................... 185
Table 7.9 8-Bit External Device/Little Endian Access and Data Alignment........................... 186
Table 7.10 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (1)-1.................................................................. 201
Table 7.11 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (2)-1.................................................................. 203
Table 7.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (3)..................................................................... 205
Table 7.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (4)-1.................................................................. 206
Table 7.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (5)-1.................................................................. 208
Table 7.15 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (6)-1.................................................................. 210
Table 7.16 Relationship between Access Size and Number of Bursts .................................. 212
Table 7.17 Access Address in SDRAM Mode Register Write ............................................. 229
Table 7.18 Relationship between Bus Width, Access Size, and Number of Bursts............... 232
Section 8 Direct Memory Access Controller (DMAC)
Table 8.1 Pin Configuration ................................................................................................. 241
Table 8.2 Transfer Request Sources ..................................................................................... 251
Table 8.3 Selecting External Request Modes with RS Bits.................................................... 254
Table 8.4 Selecting External Request Detection with DL, DS Bits ........................................ 255
Table 8.5 Selecting External Request Detection with DO Bit................................................ 255
Table 8.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits......... 256
Table 8.7 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits......... 256
Table 8.8 Supported DMA Transfers.................................................................................... 260
Table 8.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category......... 266
Section 9 Clock Pulse Generator (CPG)
Table 9.1 Clock Pulse Generator Pins and Functions ............................................................ 274
Table 9.2 Clock Operating Modes........................................................................................ 275
Table 9.3 Possible Combination of Clock Modes and FRQCR Values .................................. 276
Section 11 Power-Down Modes
Table 11.1 States of Power-Down Modes ........................................................................... 294
Rev. 2.00, 09/03, page xliii of xlvi