HD6417705F133V Datasheet, PDF (290/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

3. Channel 2
• DMA source address register_2 (SAR_2)
• DMA destination address register_2 (DAR_2)
• DMA transfer count register_2 (DMATCR_2)
• DMA channel control register_2 (CHCR_2)
4. Channel 3
• DMA source address register_3 (SAR_3)
• DMA destination address register_3 (DAR_3)
• DMA transfer count register_3 (DMATCR_3)
• DMA channel control register_3 (CHCR_3)
5. Common
• DMA operation register (DMAOR)
• DMA extended resource selector 0 (DMARS0)
• DMA extended resource selector 1 (DMARS1)
8.3.1 DMA Source Address Registers (SAR)
SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer.
During a DMA transfer, these registers indicate the next source address. When the data of an
external device with DACK is transferred in single address mode, SAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary must be set for the source address
value. The initial value is undefined. The SAR retains the current value in software standby or
module standby mode.
8.3.2 DMA Destination Address Registers (DAR)
DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer.
During a DMA transfer, these registers indicate the next destination address. When the data of an
external device with DACK is transferred in single address mode, DAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary must be set for the source address
value. The initial value is undefined. The DAR retains the current value in software standby or
module standby mode.
Rev. 2.00, 09/03, page 242 of 690