HD6417705F133V Datasheet, PDF (235/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.6 Normal Space Interface
7.6.1 Basic Timing
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 7.10, Byte-Selection SRAM Interface. Figures 7.3 and 7.4 show the basic timings of
normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is
asserted for one cycle to indicate the start of a bus cycle.
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WEn
signal for the byte to be written is asserted.
Read/write for cache fill or writeback follows the selected bus width and transfers a total of 16
bytes continuously. The bus is not released during this transfer. For cache misses that occur during
byte or word operand accesses or branching to odd word boundaries, the fill is always performed
by longword accesses on the chip-external interface. Write-through-area write access and non-
cacheable read/write access are based on the actual address size.
It is necessary to output the read out data by using RD when a buffer is established in the data bus.
The RD/WR signal is in a read state (high output) when an access is not performed. Therefore,
care must be taken about the collision of output in controlling the external data buffer.
When the WM bit in CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate an external
wait. When the WM bit in CSnWCR is set to 1, an external wait is ignored and no Tnop cycle is
inserted.
Rev. 2.00, 09/03, page 187 of 690