HD6417705F133V Datasheet, PDF (281/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.10 Byte-Selection SRAM Interface
The byte-selection SRAM interface is for outputting the byte-selection signal (WEn) in both read
and write bus cycles. This interface has 16-bit data pins and accesses SRAM that has an upper
byte-selection pin and a lower byte-selection pin, such as UB and LB. The write access timing is
the same as that for the normal space interface. The read access timing differs from that for the
normal space interface in the WEn timing, and a byte-selection signal is output from the WEn pin.
The basic access timing is shown in figure 7.31.
Note that in a write cycle, data is written in accordance with the byte-selection pin (WEn) timing.
Check the data sheet of the memory to be used for the actual timing.
T₁
T₂
CKIO
A25 to A0
CSn
WEn
RD/WR
Read
RD
D31 to D0
Write
RD/WR
RD
High
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 7.31 Byte-Selection SRAM Basic Access Timing
Rev. 2.00, 09/03, page 233 of 690