HD6417705F133V Datasheet, PDF (249/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 7.10 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex
Output (1)-1
Setting
A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0]
11 (32 bits) 00 (11 bits)
00 (8 bits)
Output Pin of Row Address Column Address Synchronous DRAM
This LSI
Output Cycle Output Cycle
Pin
Function
A17
A25
A17
Unused
A16
A24
A16
A15
A23
A15
A14
A22^*2
A22^*2
A13
A21^*2
A21^*2
A12
A20
L/H^*1
A12 (BA1)
A11 (BA0)
A10/AP
Specifies bank
Specifies
address/precharge
A11
A19
A11
A9
Address
A10
A18
A10
A8
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
A9
A1
Unused
A0
A8
A0
Example of connected memory
64-Mbit product (512 kwords x 32 bits x 4 banks, column 8 bits product): 1 device
16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 2 devices
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
Rev. 2.00, 09/03, page 201 of 690