HD6417705F133V Datasheet, PDF (122/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
31 to 9
Bit
Name

8
SV
7, 6

5, 4
RC
3

2
TF
1
IX
0
AT
Initial
Value
0

0
0
0
0
0
0
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Single Virtual Memory Mode
0: Multiple virtual memory mode
1: Single virtual memory mode
Reserved
These bits are always read as 0. The write value
should always be 0.
Random Counter
A 2-bit random counter that is automatically updated
by hardware according to the following rules in the
event of an MMU exception.
When a TLB miss exception occurs, all of TLB entry
ways corresponding to the virtual address at which
the exception occurred are checked. If all ways are
valid, 1 is added to RC; if there is one or more invalid
way, they are set by priority from way 0, in the order
way 0, way 1, way 2, and way 3. In the event of an
MMU exception other than a TLB miss exception, the
way which caused the exception is set in RC.
Reserved
These bits are always read as 0. The write value
should always be 0.
TLB Flush
Write 1 to flush the TLB (clear all valid bits of the TLB
to 0). When they are read, 0 is always returned.
Index Mode
0: VPN bits 16 to 12 are used as the TLB index
number.
1: The value obtained by EX-ORing ASID bits 4 to 0
in PTEH and VPN bits 16 to 12 is used as the TLB
index number.
Address Translation
Enables/disables the MMU.
0: MMU disabled
1: MMU enabled
Rev. 2.00, 09/03, page 74 of 690