HD6417705F133V Datasheet, PDF (225/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Description
2

0
R
Reserved
This bit is always read as 0. The write value should always be
0.
1
A3COL1 0
R/W Number of Bits of Column Address for Area 3
0
A3COL0 0
R/W Specifies the number of bits of the column address for area 3.
00: 8 bits
01: 9 bits
10: 10 bits
11: Setting prohibited
7.4.5 Refresh Timer Control/Status Register (RTCSR)
RTCSR specifies various items about refresh for SDRAM.
This register only accepts 32-bit writing to prevent incorrect writing. In this case, the upper 16 bits
of the data must be H'A55A, otherwise writing cannot be performed. When reading, the upper 16
bits are read as H'0000.
RTCSR
Bit
Bit Name
31 to 8 
7
CMF
6
CMIE
Initial
Value R/W
0
R
0
R/W
0
R/W
Description
Reserved
Compare Match Flag
0: Clearing condition When 0 is written in CMF after reading
out RTCSR during CMF = 1.
1: Setting condition When the condition RTCNT = RTCOR is
satisfied.
CMF Interrupt Enable
0: CMF interrupt request is disabled.
1: CMF interrupt request is enabled.
Rev. 2.00, 09/03, page 177 of 690