HD6417705F133V Datasheet, PDF (166/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

5.3 Individual Exception Operations
This section describes the conditions for specific exception handling and the processor operations
for resets and general exceptions. For interrupts, refer to section 6, Interrupt Controller (INTC).
5.3.1 Resets
Power-On Reset:
• Conditions
Power-on reset is request
• Operations
Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
Manual Reset:
• Conditions
Manual reset is request
• Operations
Set EXPEVT to H'020, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
5.3.2 General Exceptions
CPU Address Error:
• Conditions
 Instruction is fetched from odd address (4n + 1, 4n + 3)
 Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
 The area ranging from H'80000000 to H'FFFFFFFF in logical space is accessed in user
mode
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
Rev. 2.00, 09/03, page 118 of 690