HD6417705F133V Datasheet, PDF(19/741 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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HD6417705F133V Datasheet, PDF (19/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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Item

Page Revisions (See Manual for Details)

25.3.4 Basic Timing

642

Figure 25.18 Basic Bus

Cycle (One External Wait)

Note *2 added

tWED

WEn *2

tWED

tAH

Write

tWDD1

tWDH1

D31 to D0

Figure 25.19 Basic Bus 643

Cycle (One Software Wait,

External Wait Enabled

(WM Bit = 0), No Idle Cycle

Setting)

Notes: 1. DACKn is a waveform when active-low is specified.

2. Output timing is the same when reading byte-selection SRAM.

Note *2 added

tWED

WEn*2

Write

tWDD1

D15 to D0

tWED

tAH

tWED

tWDH1

tWDD1

tWED

tAH

tWDH1

25.3.11 SCIF Module

671

Signal Timing

Table 25.13 SCIF Module

Signal Timing

A. I/O Port States in Each 679

Processing State

Table A.1 I/O Port States

in Each Processing State

Notes: 1. DACKn is a waveform when active-low is specified.

2. Output timing is the same when reading byte-selection SRAM.

Item amended

Transmission data delay time (clock synchronization)

RTS delay time (clock synchronization)

Note *11 added

Reset

Power-Down

States

Category Pin

System RESETP

control

RESETM

Power-

Bus

on

Manual Software

Mastership

Reset Reset Standby Sleep Released I/O

I*11

I*11

I*11

I*11

I*11

I

I

I

I

I

I

I

Handling

of Unused

Pins

Must be

used

Pull-up

Rev. 2.00, 09/03, page xvii of xlvi

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