HD6417705F133V Datasheet, PDF (287/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 Direct Memory Access Controller (DMAC)
This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place
of the CPU to perform high-speed transfers between external devices with DACK (transfer request
acknowledge signal), external memory, memory-mapped external devices, and on-chip peripheral
modules.
8.1 Features
• Four channels (two channels can receive an external request)
• 4-Gbyte physical address space
• Data transfer unit: Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword × 4)
• Maximum transfer count: 16777216 transfers
• Address mode: Dual address mode or single address mode can be selected.
• Transfer requests: External request, on-chip peripheral module request, or auto request can be
selected.
The following modules can issue an on-chip peripheral module request.
SCIF0, SCIF2, CMT, USB, and A/D converter
• Bus modes: Cycle steal mode (normal mode and intermittent mode 16/64) or burst mode can
be selected.
• Selectable channel priority levels:
The channel priority levels are selectable between fixed mode and round-robin mode.
• Interrupt request: An interrupt request can be generated to the CPU after transfers end.
• External request detection: Low-/high-level or rising/falling edge detection of DREQ input can
be selected.
• Transfer request acknowledge signal: Active levels for DACK can be set independently.
• Transfer end signal: Active level for TEND can be set. TEND is output at the same timing as
DACK in the last DMA transfer. (Only channel 0)
DMAS311B_000020020100
Rev. 2.00, 09/03, page 239 of 690