HD6417705F133V Datasheet, PDF (703/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
Td1 Td2 Td3 Td4
Tc1
Tc2 Tc3
Tc4
Tde
A25 to A0
A12/A11^*1
t_AD1
t_AD1
Column
address
(1-4)
t_AD1
Read command
t_AD1
t_AD1
t_AD1
CSn
RD/WR
RASU/L
CASU/L
DQMxx
t_CSD1
t_RWD1
t_RASD1
t_CASD1
t_DQMD1
D31 to D0
t_BSD
BS
CKE
DACKn^*2
t_DACD
t_CASD1
t_CSD1
t_CSD1
t_RWD1
t_RASD1
t_CASD1
t_DQMD1 t_DQMD1
t_RDS2 t_RDH2
t_BSD
t_RDS2 t_RDH2
t_BSD
(High)
t_DACD
t_DACD
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: READ Command, Same Row Address,
CAS Latency = 2, TRCD = 1 Cycle)
Rev. 2.00, 09/03, page 655 of 690