HD6417705F133V Datasheet, PDF (334/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figures 10.1 shows a block diagram of the WDT.
Standby
cancellation
Internal
reset
request
Interrupt
request
Standby
control
WDT
Reset
control
Interrupt
control
Divider
Clock selection
Overflow
Clock selector
Clock
WTCSR
WTCNT
Bus interface
Standby
mode
Peripheral
clock
Legend
WTCSR:
WTCNT:
Watchdog timer control/status register
Watchdog timer counter
Figure 10.1 Block Diagram of WDT
10.2 Register Descriptions
The WDT has the following two registers. Refer to section 24, List of Registers for the details of
the addresses of these registers and the state of registers in each operating mode.
• Watchdog timer counter (WTCNT)
• Watchdog timer control/status register (WTCSR)
10.2.1 Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit readable/writable register that increments on the
selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an
interrupt in interval timer mode. The WTCNT counter is not initialized by an internal reset due to
the WDT overflow. The WTCNT counter is initialized to H'00 only by a power-on reset using the
RESETP pin.
Use a word access to write to the WTCNT counter, with H'5A in the upper byte. Use a byte access
to read WTCNT.
Rev. 2.00, 09/03, page 286 of 690