HD6417705F133V Datasheet, PDF (159/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

5.1.2 Exception Event Register (EXPEVT)
EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception
codes to be specified in EXPEVT are those for resets and general exceptions. These exception
codes are automatically specified the hardware when an exception occurs. Only bits 11 to 0 of
EXPEVT can be re-written using the software.
Bit
Bit Name Initial Value R/W Description
31 to 12 
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0 EXPEVT *
R/W 12-bit Exception Code
Note: * Initialized to H'000 at power-on reset and H'020 at manual reset.
5.1.3 Interrupt Event Register (INTEVT)
INTEVT is assigned to address H'FFFFFFD8 and consists of a 12-bit exception code. Exception
codes to be specified in INTEVT are those for interrupt requests. These exception codes are
automatically specified by the hardware when an exception occurs. Only bits 11 to 0 of INTEVT
can be re-written using the software.
Bit
Bit Name
31 to 12 
11 to 0 INTEVT
Initial Value R/W
0
R

R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit Exception Code
Rev. 2.00, 09/03, page 111 of 690