HD6417705F133V Datasheet, PDF (23/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

5.1.3 Interrupt Event Register (INTEVT).................................................................. 111
5.1.4 Interrupt Event Register 2 (INTEVT2)............................................................. 112
5.1.5 Exception Address Register (TEA) .................................................................. 112
5.2 Exception Handling Function ....................................................................................... 113
5.2.1 Exception Handling Flow ................................................................................ 113
5.2.2 Exception Vector Addresses ............................................................................ 114
5.2.3 Exception Codes.............................................................................................. 114
5.2.4 Exception Request and BL Bit (Multiple Exception Prevention)....................... 114
5.2.5 Exception Source Acceptance Timing and Priority........................................... 115
5.3 Individual Exception Operations .................................................................................. 118
5.3.1 Resets.............................................................................................................. 118
5.3.2 General Exceptions.......................................................................................... 118
5.3.3 General Exceptions (MMU Exceptions)........................................................... 121
5.4 Usage Notes................................................................................................................. 124
Section 6 Interrupt Controller (INTC)............................................................ 125
6.1 Features ....................................................................................................................... 125
6.2 Input/Output Pins......................................................................................................... 127
6.3 Register Descriptions ................................................................................................... 127
6.3.1 Interrupt Priority Level Setting Registers A to H (IPRA to IPRH)..................... 128
6.3.2 Interrupt Control Register 0 (ICR0).................................................................. 129
6.3.3 Interrupt Control Register 1 (ICR1).................................................................. 130
6.3.4 Interrupt Control Register 2 (ICR2).................................................................. 132
6.3.5 PINT Interrupt Enable Register (PINTER) ....................................................... 132
6.3.6 Interrupt Request Register 0 (IRR0) ................................................................. 133
6.3.7 Interrupt Request Register 1 (IRR1) ................................................................. 134
6.3.8 Interrupt Request Register 2 (IRR2) ................................................................. 135
6.4 Interrupt Sources.......................................................................................................... 136
6.4.1 NMI Interrupt.................................................................................................. 136
6.4.2 IRQ Interrupts ................................................................................................. 136
6.4.3 IRL Interrupts.................................................................................................. 137
6.4.4 PINT Interrupt................................................................................................. 138
6.4.5 On-Chip Peripheral Module Interrupts ............................................................. 138
6.4.6 Interrupt Exception Handling and Priority........................................................ 139
6.5 Operation..................................................................................................................... 144
6.5.1 Interrupt Sequence........................................................................................... 144
6.5.2 Multiple Interrupts........................................................................................... 147
6.6 Usage Note .................................................................................................................. 147
Section 7 Bus State Controller (BSC) ............................................................ 149
7.1 Overview ..................................................................................................................... 149
7.1.1 Features........................................................................................................... 149
7.1.2 Block Diagram ................................................................................................ 150
Rev. 2.00, 09/03, page xxi of xlvi