HD6417705F133V Datasheet, PDF (410/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

15.3.13 Date Alarm Register (RDAYAR)
The date alarm register (RDAYAR) is an 8-bit readable/writable register, and an alarm register
corresponding to the date counter RDAYCNT. When the ENB bit is set to 1, a comparison with
the RDAYCNT value is performed. For alarm registers RSECAR, RMINAR, RHRAR, RWKAR,
RDAYAR, and RMONAR, a comparison with the corresponding counter value is performed for
those whose ENB bit is set to 1, and for RCR3, a comparison is performed when the YAEN bit is
set to 1. If all of those match, an RTC alarm interrupt is generated.
The range of date alarm that can be set is 01 to 31 (decimal). Errant operation will result if any
other value is set. The RDAYCNT range that can be set changes with some months and in leap
years. Please confirm the correct setting.
The ENB bit in RDAYAR is initialized by a power-on reset, and it is not initialized by manual
reset and standby mode. The remaining RDAYAR fields are not initialized by a power-on reset or
manual reset, or in standby mode.
Bit
7
6
5, 4
3 to 0
Bit Name
ENB
Initial Value R/W
0
R/W

0
R


R/W


R/W
Description
Date Alarm Enable
Specifies whether to compare RDAYCNT with
RDAYAR to generate a second alarm.
0: Not compared
1: Compared
Reserved
This bit is always read as 0. The write value
should always be 0.
10-unit of date alarm setting in the BCD-code.
The range that can be set is 0 to 3 (decimal).
1-unit of date alarm setting in the BCD-code.
The range that can be set is 0 to 9 (decimal).
Rev. 2.00, 09/03, page 362 of 690