SH7144 Datasheet, PDF (87/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Section 4 Clock Pulse Generator
This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ)and the
peripheral clock(Pφ), and then makes internal clock (φ/2 to φ/8192 and Pφ/2 to Pφ/1024) out of
this generated clock. The CPG consists of an oscillator, PLL circuit, and pre-scaler. A block
diagram of the clock pulse generator is shown in figure 4.1. The frequency from the oscillator can
be modified by the PLL circuit.
PLLCAP
CK
EXTAL
XTAL
Oscillator PLL circuit
Clock divider
(× 1/2)
MD2
MD3
Clock mode
control circuitry
Pre-scaler
Pre-scaler
φ
φ/2 to
Pφ/2 to
Pφ
φ/8192
Pφ/1024
for internal circuit
Figure 4.1 Block Diagram of the Clock Pulse Generator
CPG0111A_010020020700
Rev. 2.0, 09/02, page 47 of 732