SH7144 Datasheet, PDF (200/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W Description
1
NMIF
0
R/(W)* NMI Flag
Indicates input of an NMI. This bit is set
irrespective of whether the DMAC is operating or
suspended. If this bit is set during a data transfer,
transfers on all channels are suspended. The CPU
is unable to write a 1 to the NMIF. Clearing is
effected by a 0 write after 1 read.
0: No NMI interrupt, DMA transfer enabled
Clearing condition:
Write NMIF = 0 after reading NMIF = 1
1: NMI has occurred, DMA transfer prohibited
Set condition:
NMI interrupt occurrence
0
DME
0
R/W DMAC Master Enable
This bit enables activation of the entire DMAC.
When the DME bit and DE bit of the CHCR for the
corresponding channel are set to 1, that channel is
transfer-enabled. If this bit is cleared during a data
transfer, transfers on all channels are suspended.
0: Disable operation on all channels
1: Enable operation on all channels
Even when the DME bit is set, when the TE bit of
the CHCR is 1, or its DE bit is 0, transfer is
disabled when NMI of the DMAOR = 1 or when AE
= 1.
Note: * Only 0 can be written to clear the flag.
Rev. 2.0, 09/02, page 160 of 732