SH7144 Datasheet, PDF (318/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

TGRA_3
TCDR
T1 period
c
T2 period
ad
b
T1 period
TDDR
H'0000
Positive phase
Negative phase
Figure 11.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5)
Complementary PWM Mode 0% and 100% Duty Output: In complementary PWM mode, 0%
and 100% duty cycles can be output as required. Figures 11.43 to 11.47 show output examples.
100% duty output is performed when the data register value is set to H'0000. The waveform in this
case has a positive phase with a 100% on-state. 0% duty output is performed when the data
register value is set to the same value as TGRA_3. The waveform in this case has a positive phase
with a 100% off-state.
On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off
compare-match for the same phase occur simultaneously, both compare-matches are ignored and
the waveform does not change.
Toggle Output Synchronized with PWM Cycle: In complementary PWM mode, toggle output
can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in
the timer output control register (TOCR). An example of a toggle output waveform is shown in
figure 11.48.
This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match
between TCNT4 and H'0000.
The output pin for this toggle output is the TIOC3A pin. The initial output is 1.
Rev. 2.0, 09/02, page 278 of 732