SH7144 Datasheet, PDF(204/773 Page) Renesas Technology Corp – Hitachi SuperH RISC engine

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SH7144 Datasheet, PDF (204/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

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= 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer

request signal.

The transfer request source need not be the data transfer source or transfer destination. However,

when the transfer request is set by RXI (transfer request because SCIâs receive data is full), the

transfer source must be the SCIâs receive data register (RDR). When the transfer request is set by

TXI (transfer request because SCIâs transmit data is empty), the transfer destination must be the

SCIâs transmit data register (TDR). Also, if the transfer request is set to the A/D converter, the

data transfer destination must be the A/D converter register.

Table 10.3 Selecting On-Chip Peripheral Module Request Modes with the RS Bits

DMAC Transfer

RS3 RS2 RS1 RS0 Request Source

DMA Transfer

Desti-

Request Signal Source nation Bus Mode

0 1 1 0 MTU

TGIA_0

Any* Any* Burst/cycle steal

0 1 1 1 MTU

TGIA_1

Any* Any* Burst/cycle steal

1 0 0 0 MTU

TGIA_2

Any* Any* Burst/cycle steal

1 0 0 1 MTU

TGIA_3

Any* Any* Burst/cycle steal

1 0 1 0 MTU

TGIA_4

Any* Any* Burst/cycle steal

1 0 1 1 A/D1

ADI1

ADDR1 Any* Burst/cycle steal

1 1 0 0 SCI0 transmit block TXI_0

Any* TDR0 Burst/cycle steal

1 1 0 1 SCI0 receiver block RXI_0

RDR0 Any* Burst/cycle steal

1 1 1 0 SCI1 transmit block TXI_1

Any* TDR1 Burst/cycle steal

1 1 1 1 SCI1 receiver block RXI_1

RDR1 Any* Burst/cycle steal

Notes: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral

module (excluding DMAC, DTC, BSC, UBC).

MTU: Multifunction timer pulse unit.

SCI0, SCI1: Serial communications interface channels 0 and 1.

ADDR1: A/D converterâs A/D register.

TDR_0, TDR_1: SCI_0 and SCI_1 transmit data registers.

RDR_0, RDR_1: SCI_0 and SCI_1 receive data registers.

In order to output a transfer request from an on-chip peripheral module, set the relevant interrupt

enable bit for each module, and output an interrupt signal.

When an on-chip peripheral moduleâs interrupt request signal is used as a DMA transfer request

signal, interrupts for the CPU are not generated.

When a DMA transfer is conducted corresponding with one of the transfer request signals in table

10.3, it is automatically discontinued. In cycle steal mode this occurs in the first transfer, and in

burst mode in the last transfer.

Rev. 2.0, 09/02, page 164 of 732

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