SH7144 Datasheet, PDF (44/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

MD3
MD2
MD1
MD0
NMI
EXTAL
XTAL
PLLVcc
PLLCAP
PLLVss
FWP*
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
AVcc
AVref
AVss
DBGMD
PC15/A15
PC14/A14
PC13/A13
PC12/A12
PC11/A11
PC10/A10
;;;; _AUD*
Flash ROM/
mask ROM
256kB
RAM
8kB
;^;;^;;;^;; _P
L
Data transfer
L
Controller
CPU
Direct memory
access controller
;;;;;;;; Interrupt Userbreak
controller controller
Bus state
controller
;;^{; Serial communication}
interface
( 4 channels)
Compare match
timer
( 2 channels)
Multifunction
timer pulse unit
A/D
Watchdog
converter timer
;;;;;;;;;;;_;; ^{I2C bus interface}
H-UDI*
PC9/A9
PC8/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
PD31/D31/
PD30/D30/
PD29/D29/
PD28/D28/
PD27/D27/DACK1
PD26/D26/DACK0
PD25/D25/
PD24/D24/
PD23/D23/ /
PD22/D22/ /AUDCK
PD21/D21/ /AUDMD
PD20/D20/ /
PD19/D19/ /AUDATA3
PD18/D18/ /AUDATA2
PD17/D17/ /AUDATA1
PD16/D16/ /AUDATA0
PD15/D15
PD14/D14
PD13/D13
PD12/D12
PD11/D11
PD10/D10
PD9/D9
PD8/D8
PD7/D7
PD6/D6
PD5/D5
PD4/D4
PD3/D3
PD2/D2
PD1/D1
PD0/D0
Peripheral address bus (12bits)
Peripheral data bus (16bits)
Internal address bus (32bits)
Internal upper data bus (16bits)
Internal lower data bus (16bits)
Note: Modules for the F-ZTAT reision only
Figure 1.2 Block Diagram of SH7145
Rev. 2.0, 09/02, page 4 of 732