SH7144 Datasheet, PDF (134/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit
UBAMRH
Bit 15 to 0
UBAMRL
Bit 15 to 0
Bit Name Initial Value R/W
UBM31 to All 0
R/W
UBM16
UBM15 to All 0
R/W
UBM0
Description
User Break Address Mask 31 to 16
0: Corresponding UBA bit is included in the
break conditions
1: Corresponding UBA bit is not included in
the break conditions
User Break Address Mask 15 to 0
0: Corresponding UBA bit is included in the
break conditions
1: Corresponding UBA bit is not included in
the break conditions
7.2.3 User Break Bus Cycle Register (UBBR)
The user break bus cycle register (UBBR) is a 16-bit readable/writable register that sets the four
break conditions.
Bit
Bit Name Initial Value R/W
15 to 8 —
All 0
R
7
CP1
0
R/W
6
CP0
0
R/W
5
ID1
0
R/W
4
ID0
0
R/W
Description
Reserved bits
These bits are always read as 0. The write value
should always be 0.
CPU Cycle/DMAC, DTC Cycle Select 1 and 0
These bits specify break conditions for CPU cycles or
DMAC/DTC cycles.
00: No user break interrupt occurs
01: Break on CPU cycles
10: Break on DTC or DMAC cycles
11: Break on both CPU and DMAC or DTC cycles
Instruction Fetch/Data Access Select1 and 0
These bits select whether to break on instruction fetch
and/or data access cycles.
00: No user break interrupt occurs
01: Break on instruction fetch cycles
10: Break on data access cycles
11: Break on both instruction fetch and data access
cycles
Rev. 2.0, 09/02, page 94 of 732