SH7144 Datasheet, PDF (173/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W Description
13 IW21
1
12 IW20
1
R/W Idle cycles in CS2 space cycles
R/W _{These bits insert idle cycles when the write cycle to the}
CS2 space comes after read access to the CS2 space, or
when continuous access is made to different CS spaces
after read access to the CS2 space.
00: No idle cycle inserted after access to the CS2 space
01: One idle cycle inserted after access to the CS2 space
10: Two idle cycles inserted after access to the CS2 space
11: Three idle cycles inserted after access to the CS2
space
11 IW11
1
10 IW10
1
R/W Idle cycles in CS1 space cycles
R/W _{These bits insert idle cycles when the write cycle to the}
CS1 space comes after read access to the CS1 space, or
when continuous access is made to different CS spaces
after read access to the CS1 space.
00: No idle cycle inserted after access to the CS1 space
01: One idle cycle inserted after access to the CS1 space
10: Two idle cycles inserted after access to the CS1 space
11: Three idle cycles inserted after access to the CS1
space
9
IW01
1
8
IW00
1
R/W Idle cycles in CS0 space cycles
R/W _{These bits insert idle cycles when the write cycle to the}
CS0 space comes after read access to the CS0 space, or
when continuous access is made to different CS spaces
after read access to the CS0 space.
00: No idle cycle inserted after access to the CS0 space
01: One idle cycle inserted after access to the CS0 space
10: Two idle cycles inserted after access to the CS0 space
11: Three idle cycles inserted after access to the CS0
space
Rev. 2.0, 09/02, page 133 of 732