SH7144 Datasheet, PDF (55/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

2.2.2 Control Registers
The control registers consist of three 32-bit registers: status register (SR), global base register
(GBR), and vector base register (VBR). The status register indicates processing states. The global
base register functions as a base address for the indirect GBR addressing mode to transfer data to
the registers of on-chip peripheral modules. The vector base register functions as the base address
of the exception processing vector area (including interrupts).
Status Register (SR):
Bit Bit Name Initial Value R/W Description
31 —
0
R/W Reserved bits.
30 —
0
29 —
0
R/W This bit is always read as 0. The write value should
R/W ^{always be 0.}
28 —
0
R/W
27 —
0
R/W
26 —
0
R/W
25 —
0
R/W
24 —
0
R/W
23 —
0
R/W
22 —
0
R/W
21 —
0
R/W
20 —
0
R/W
19 —
0
R/W
18 —
0
R/W
17 —
0
R/W
16 —
0
R/W
15 —
0
R/W
14 —
0
R/W
13 —
0
R/W
12 —
0
R/W
11 —
0
R/W
10 —
0
R/W
9
M
Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions.
8
Q
Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions.
Rev. 2.0, 09/02, page 15 of 732