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SH7144 Datasheet, PDF (75/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine | |||
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Instruction
Instruction Code
Operation
Execution
States T Bit
DT
Rn
0100nnnn00010000
Rn â 1 â Rn, when Rn 1
is 0, 1 â T. When Rn is
nonzero, 0 â T
Comparison
result
EXTS.B Rm,Rn
0110nnnnmmmm1110 Byte in Rm is sign-
1
â
extended â Rn
EXTS.W Rm,Rn
0110nnnnmmmm1111 Word in Rm is sign- 1
â
extended â Rn
EXTU.B Rm,Rn
0110nnnnmmmm1100 Byte in Rm is zero-
1
â
extended â Rn
EXTU.W Rm,Rn
0110nnnnmmmm1101 Word in Rm is zero- 1
â
extended â Rn
MAC.L
@Rm+,@Rn+ 0000nnnnmmmm1111
Signed operation of
(Rn) Ã (Rm) + MAC â
MAC 32 Ã 32 + 64 â
64 bits
3/(2 to 4)* â
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of 3/(2)*
â
(Rn) Ã (Rm) + MAC â
MAC 16 Ã 16 + 64 â
64 bits
MUL.L Rm,Rn
0000nnnnmmmm0111 Rn à Rm â MACL,
32 Ã 32 â 32 bits
2 to 4* â
MULS.W Rm,Rn
0010nnnnmmmm1111 Signed operation of 1 to 3* â
Rn à Rm â MACL 16 Ã
16 â 32 bits
MULU.W Rm,Rn
0010nnnnmmmm1110 Unsigned operation of 1 to 3* â
Rn à Rm â MACL 16 Ã
16 â 32 bits
NEG
Rm,Rn
0110nnnnmmmm1011 0 â Rm â Rn
1
â
NEGC Rm,Rn
0110nnnnmmmm1010 0 â Rm â T â Rn,
1
Borrow â T
Borrow
SUB
Rm,Rn
0011nnnnmmmm1000 Rn â Rm â Rn
1
â
SUBC Rm,Rn
0011nnnnmmmm1010 Rn â Rm â T â Rn, 1
Borrow â T
Borrow
SUBV Rm,Rn
0011nnnnmmmm1011 Rn â Rm â Rn,
1
Underflow â T
Overflow
Note: * The normal number of execution states is shown. (The number in parentheses is the
number of states when there is contention with the preceding or following instructions.)
Rev. 2.0, 09/02, page 35 of 732
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