SH7144 Datasheet, PDF (765/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Item
Page
Table 26.6 Bus Timing 675
Table 26.7 Direct
679
Memory Access
Controller Timing
Table 26.8 Multi-
681
Function Timer Pulse
Unit Timing
Table 26.9 I/O Port
682
Timing
Revisions (See Manual for Details)
Min and Max values amended.
Item
Symbol Min
Write data delay time t_WDD
WAIT setup time
t
WTS
WAIT hold time
t
WTH
Read data access
t
ACC
time

12
3
t_cyc×(n+2)−35
Access time from
t_OE
read strobe
t_cyc×(n+1.5)−33
Max
30




Item and Min values amended.
Item
Symbol
DREQ0, DREQ1 setup
t_DRQS
time
DREQ0, DREQ1 hold time t_DRQH
Min
Max
10

1.5 t_cyc−10 
Min values amended.
Item
Input capture input setup time
Timer input setup time
Symbol
t
TICS
t
TCKS
Min
19
19
Max


Min values description of operating precautions amended.
Item
Symbol
Min
Port output data delay time
t_PWD

Port input hold time
t_PRH
19
Port input setup time
t_PRS
19
[Operating precautions]
The port input signals are asynchronous. They are, however,
considered to have been changed at CK clock fall with two-
state intervals shown in figure 26.17. If the setup times
shown here are not observed, recognition may be delayed
until the clock fall two states after that timing.
Rev. 2.0, 09/02, page 725 of 732