SH7144 Datasheet, PDF (628/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Write pulse application subroutine
Apply Write Pulse
Enable WDT
Set PSU bit in FLMCR1
Wait (tspsu) µs
Set P bit in FLMCR1
Wait (tsp10, tsp30, or tsp200) µs
Clear P bit in FLMCR1
Wait (tcp) µs
Start of programming
START
Set SWE bit in FLMCR1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Wait (tsswe) µs
*7
*7
Store 128-byte program data in program
data area and reprogram data area
*4
Start of programming
n=1
m=0
*5*7
Successively write 128-byte data from reprogram
End of programming ^{data area in RAM to flash memory}
*1
Sub-Routine-Call
*7
Apply Write Pulse (tsp30 or tsp200)
See note *6 for pulse width
Clear PSU bit in FLMCR1
Wait (tcpsu) µs
*7
Disable WDT
End Sub
Set PV bit in FLMCR1
Wait (tspv) µs
*7
H'FF dummy write to verify address
Wait (tspvr) µs
*7
Read verify data
*2
Note: 6. Write Pulse Width
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
Write Time (tsp) µs
tsp30
tsp30
tsp30
tsp30
tsp30
tsp30
tsp200
tsp200
tsp200
tsp200
tsp200
tsp200
tsp200
Increment address
998
999
1000
tsp200
tsp200
tsp200
* Use a tsp10 write pulse for additional programming.
Write data =
NG
verify data?
OK
NG
6≥n?
OK
Additional-programming data computation
m=1
Transfer additional-programming data to
additional-programming data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram data area
*4
128-byte
NG
data verification completed?
OK
Clear PV bit in FLMCR1
Wait (tcpv) µs
*7
RAM
Program data storage
area (128 bytes)
NG
6 ≥ n?
OK
Successively write 128-byte data from additional-
programming data area in RAM to flash memory ^*1
Apply Write Pulse (tsp10) (Additional programming)
n←n+1
Reprogram
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
NG
m=0?
OK
Clear SWE bit in FLMCR1
Wait (tcswe) µs
End of programming
*7 _NG
n ≥ N?
OK
Clear SWE bit in FLMCR1
Wait (tcswe) µs
*7
Programming failure
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the start address to be written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 32-bit (longword) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the subsequent verify operation ends in failure.
4. A 128-byte area for the storage of programming data, a 128-byte area for the storage of reprogramming data, and a 128-byte area for the storage of additional-
programming data must be provided in RAM. The contents of the reprogram data area and additional-program data area are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See note 6 for details of the pulse widths. When writing of
additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
7. The wait times and value of N are shown in section 26.5, Flash Memory Characteristics.
Reprogram Data Computation Table
Additional-Programming Data Computation Table
Original Data
(D)
0
Verify Data
(V)
0
0
1
1
0
1
1
Reprogram Data
(X)
1
0
1
1
Comments
Programming completed
Programming incomplete;
reprogram
Still in erased state; no action
Reprogram Data
(X')
0
0
1
1
Verify Data
(V)
0
1
0
1
Additional-
Programming Data (Y)
0
1
1
1
Comments
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Figure 19.9 Program/Program-Verify Flowchart
Rev. 2.0, 09/02, page 588 of 732