SH7144 Datasheet, PDF (474/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

14.3.7 Serial Control Register X (SCRX)
SCRX is an 8-bit readable/writable register that controls register access and the I²C operating
mode. When the modules that are controlled by SCRX are not in use, do not write 1 to these bits.
Bit
Bit Name
7
6
5 IICX0
4 IICE
3 HNDS
Initial Value R/W
0
R
0
R
0
R/W
0
R/W
0*
R/W
Description
These bits are reserved and always return 0 when
read, and should only be written with 0.
I²C transfer-rate select 0
Along with bits CKS2 to CKS0 of ICMR, this bit selects
the transfer rate in the master mode. For details on
setting the transfer rate, refer to section 14.3.4, I²C Bus
Mode Register (ICMR).
I²C master enable
This bit controls access by the CPU to the data register
and control registers (ICCR, ICSR, ICDR/SARX, and
ICMR/SAR) of the I²C bus interface.
0: Disables CPU access to the data register and
control registers of the I²C bus interface.
1: Enables CPU access to the data register and control
registers of the I²C bus interface.
Hand-shake receive bit
This bit enables/disables buffered operation in the
receive mode in the I²C bus format.
0: Enables buffered operation for reception*
Receiving of the next frame proceeds even when
ICDR contains valid received data.
1: Disables buffered operation for reception
When ICDR contains valid received data, SCL is set
to its low level and receiving of the next frame of
data is thus suspended until the received data is
read from ICDR.
Rev. 2.0, 09/02, page 434 of 732