SH7144 Datasheet, PDF (732/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

CK
(Branch trace)
AUDCK (input)
(RAM monitor)
t_cyc
t_RMCYC
t_AUDRSTW
AUDMD
t_AUDMDS
Figure 26.27 AUD Reset Timing
AUDCK
(output)
AUDATA3 to
AUDATA0
(output)
(output)
t_BTCKW
t_BTDD
t_BTSD
t_BTCYC
t_BTDH
t_BTSH
Figure 26.28 Branch Trace Timing
AUDCK
(input)
AUDATA3 to
AUDATA0
(output)
AUDATA3 to
AUDATA0
(input)
t_RMCYC
t_RMCKW
t_RMDD
t_RMDHD
t_RMDS
t_RMDH
t_RMSS
t_RMSH
(input)
Figure 26.29 RAM Monitor Timing
Rev. 2.0, 09/02, page 692 of 732