SH7144 Datasheet, PDF (492/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Start
Initial setting
Set MST=0,
TRS=0 (ICCR)
Set ACKB=0 (ICSR)
Read the IRIC flag (ICCR)
No
IRIC=1?
Yes
Read the AAS and
ADZ flags (ICSR)
AAS=1 and ^No
ADZ=0?
Yes
Read the TRS bit (ICCR)
No
TRS=0?
Yes
Final receive ^Yes
operation?
No
Read ICDR
Clear the IRIC flag (ICCR)
Read the IRIC flag (ICCR)
No
IRIC=1?
Yes
Set ACKB=0 (ICSR)
Read ICDR
Clear the IRIC flag (ICCR)
Read the IRIC flag (ICCR)
No
IRIC=1?
Yes
Read ICDR
Clear the IRIC flag (ICCR)
End
[1]
[2]
General call address processing
* Explanation omission
Slave-transmission mode
[1] Set the device to the slave-reception mode.
[2] Wait for one byte to be recieved (slave address).
[3] ^{[3] Start of reception (dummy read as the first operation).}
[4] Wait for the completion of reception.
[5] Set the acknowledgement for the final receive operation.
[4] ^{[6] Start the final receive operation.}
[7] Wait for the end of the receive operation.
[8] Read the last data to be received.
[5]
[6]
[7]
[8]
Figure 14.16 Example: Flowchart of Operations in the Slave-Reception Mode
Rev. 2.0, 09/02, page 452 of 732