SH7144 Datasheet, PDF (487/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

14.4.6 Timing for Setting IRIC and the Control of SCL
The timing with which the interrupt-request flag (IRIC) is set varies according to the settings of
the WAIT bit in ICMR, FS bit in SAR, and the FSX bit in SARX. When the TDRE and RDRF
internal flags are set to 1, the level on SCL is automatically set low in synchronization with the
internal clock after the transfer of one frame of data. Figure 14.12 shows the timing with which
IRIC is set and the control of SCL.
(a) When WAIT=0, and FS=0 or FSX=0 (I²C bus format, no wait )
SCL 7
8
9
1
SDA 7
8
A
1
IRIC
User processing
IRIC clear
ICDR write (during transmission) or
ICDR read (during reception)
(b) When WAIT=1, and FS=0 or FSX=0 (I²C bus format, wait inserted )
SCL ₈
9
1
SDA ⁸
A
1
IRIC
User processing
IRIC clear
IRIC clear ICDR write (during transmission) or
ICDR read (during reception)
(c) When FS=1 and FSX=1 (clock-synchronized serial format )
SCL 7
8
1
SDA 7
8
1
IRIC
User processing
IRIC clear
ICDR write (during transmission) or
ICDR read (during reception)
Figure 14.12 IRIC-Set Timing and the Control of SCL
Rev. 2.0, 09/02, page 447 of 732