SH7144 Datasheet, PDF (729/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

26.3.13 H-UDI Timing
Table 26.15 shows H-UDI timing.
Table 26.15 H-UDI Timing
Conditions: V_CC = PLLV_CC =3.3 V ± 0.3 V, AV_CC = 3.3 V ± 0.3 V, AV_CC = V_CC ± 0.3 V,
AV_ref = 3.0 V to AV_CC , V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications),
When programming or erasing flash memory, T_a = –20°C to +75°C.
Item
Symbol Min
TCK clock cycle
t_tcyc
60*
TCK clock high-level width
t_TCKH
0.4
TCK clock low-level width
t_TCKL
0.4
TRST pulse width
t_TRSW
20
TRST setup time
t_TRSS
30
TMS setup time
t_TMSS
15
TMS hold time
t_TMSH
10
TDI setup time
t_TDIS
15
TDI hold time
t_TDIH
10
TDO delay time
t_TDOD

Note:
*
The
value
must
not
be
under
2
×
t.
cyc
Max

0.6
0.6






30
Unit
ns
t_tcyc
t_tcyc
t_tcyc
ns
ns
ns
ns
ns
ns
Figure
Figure 26.24
Figure 26.25
Figure 26.26
TCK
t_TCKH
t_TCKL
V_IH
V_IH
V_IL
t_tcyc
V_IH
V_IL
Figure 26.24 H-UDI Clock Timing
TCK
V_IL
t_TRSS
V_IL
t_TRSS
V_IL
V_IH
t_TRSW
Figure 26.25 H-UDI TRST Timing
Rev. 2.0, 09/02, page 689 of 732