SH7144 Datasheet, PDF (270/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

11.3.11 Timer Output Control Register (TOCR)
TOCR is an 8-bit readable/writable register that enables/disables PWM synchronized toggle
output in complementary PWM mode/reset synchronized PWM mode, and controls output level
inversion of PWM output.
Bit Bit Name Initial value R/W Description
7
—
0
R
Reserved
This bit is always read as 0 and should be written with
0.
6
PSYE
0
R/W PWM Synchronous Output Enable
This bit selects the enable/disable of toggle output
synchronized with the PWM period.
0: Toggle output is disabled
1: Toggle output is enabled
5
—
0
4
—
0
3
—
0
2
—
0
R
Reserved
R
These bits are always read as 0s and should be
R
written with 0s.
R
1
OLSN
0
R/W Output Level Select N
This bit selects the reverse phase output level in
reset-synchronized PWM mode/complementary PWM
mode. See table 11.26
0
OLSP
0
R/W Output Level Select P
This bit selects the positive phase output level in
reset-synchronized PWM mode/complementary PWM
mode. See table 11.26
Table 11.26 Output Level Select Function
Bit 1
Function
Compare Match Output
OLSN Initial Output Active Level Up Count
Down Count
0
High level
Low level
High level
Low level
1
Low level
High level
Low level
High level
Note: The reverse phase waveform initial output value changes to active level after elapse of the
dead time after count start.
Rev. 2.0, 09/02, page 230 of 732