SH7144 Datasheet, PDF (238/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

11.3.1 Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR
register settings should be conducted only when TCNT operation is stopped.
Bit Bit Name Initial value R/W Description
7
CCLR2
0
R/W Counter Clear 0 to 2
6
CCLR1
0
5
CCLR0
0
R/W These bits select the TCNT counter clearing source.
R/W ^{See tables 11.3 and 11.4 for details.}
4
CKEG1 0
R/W Clock Edge 0 and 1
3
CKEG0 0
R/W These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g. Pφ/4 both edges = Pφ/2
rising edge). If phase counting mode is used on
channels 1 and 2, this setting is ignored and the
phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is
Pφ/4 or slower. When Pφ/1, or the overflow/underflow
of another channel is selected for the input clock,
although values can be written, counter operation
compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
Legend
X: Don’t care
2
TPSC2
0
R/W Time Prescaler 0 to 2
1
TPSC1
0
0
TPSC0
0
R/W These bits select the TCNT counter clock. The clock
R/W ^{source can be selected independently for each}
channel. See tables 11.5 to 11.8 for details.
Rev. 2.0, 09/02, page 198 of 732