SH7144 Datasheet, PDF (618/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W Description
7
FEW
1/0
R
Flash Write Enable*
Reflects the input level at the FWP pin. It is set to 1
when a low level is input to the FWP pin, and cleared
to 0 when a high level is input.
6
SWE
0
R/W Software Write Enable
When this bit is set to 1 while the FEW bit is 1, flash
memory programming/erasing is enabled. When this
bit is cleared to 0, other FLMCR1 bits and all EBR1
and EBR2 bits cannot be set.
5
ESU
0
R/W Erase Setup
When this bit is set to 1 while the FEW and SWE bits
are 1, the flash memory changes to the erase setup
state. When it is cleared to 0, the erase setup state is
cancelled.
4
PSU
0
R/W Program Setup
When this bit is set to 1 while the FEW and SWE bits
are 1, the flash memory changes to the program
setup state. When it is cleared to 0, the program
setup state is cancelled.
3
EV
0
R/W Erase-Verify
When this bit is set to 1 while the FEW and SWE bits
are 1, the flash memory changes to erase-verify
mode. When it is cleared to 0, erase-verify mode is
cancelled.
2
PV
0
R/W Program-Verify
When this bit is set to 1 while the FEW and SWE bits
are 1, the flash memory changes to program-verify
mode. When it is cleared to 0, program-verify mode is
cancelled.
1
E
0
R/W Erase
When this bit is set to 1 while the FEW, SWE and
ESU bits are 1, the flash memory changes to erase
mode. When it is cleared to 0, erase mode is
cancelled.
0
P
0
R/W Program
When this bit is set to 1 while the FEW, SWE and
PSU bits are 1, the flash memory changes to program
mode. When it is cleared to 0, program mode is
cancelled.
Note: * The value of this bit is 1 when using E10A (when DBGMD is high).
Rev. 2.0, 09/02, page 578 of 732