SH7144 Datasheet, PDF (521/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Section 16 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) comprising two 16-bit timer channels. The
CMT has 16-bit counters and can generate interrupts at specified intervals.
16.1 Features
The CMT has the following features:
• Four kinds of counter input clock can be selected
 One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) can be selected independently
for each channel.
• Interrupt sources
 A compare match interrupt can be requested independently for each channel.
• Module standby mode can be set
Figure 16.1 shows a block diagram of the CMT.
CMI0
Control circuit
Pφ/32 Pφ/512
Pφ/8 Pφ/128
CMI1
Clock selection
Control circuit
Pφ/32 Pφ/512
Pφ/8 Pφ/128
Clock selection
Module bus
Legend:
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
CMCOR: Compare match timer constant register
CMCNT: Compare match timer counter
CMI: Compare match interrupt
CMT
Bus
interface
Internal bus
Figure 16.1 CMT Block Diagram
TIMCMT0A_000220020700
Rev. 2.0, 09/02, page 481 of 732