SH7144 Datasheet, PDF (454/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

14.3 Description of Registers
The I²C bus interface includes the following registers. For the addresses of these registers and the
states of the registers in each state of processing, refer to section 25, List of Registers.
• I²C bus control register (ICCR)
• I²C bus status register (ICSR)
• I²C bus data register (ICDR)
• I²C bus mode register (ICMR)
• Slave-address register (SAR)
• Second slave-address register (SARX)
• Serial control register X (SCRX)
14.3.1 I²C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that holds the data for transmission during
transmission, and holds the received data during reception. Internally, ICDR consists of a shift
register (ICDRS), receive buffer (ICDRR), and transmission buffer (ICDRT).
ICDRS is the shift register and is not accessible from the CPU.
ICDRR is a read-only register; it stores data being received.
ICDRT is a write-only register; it stores data for transmission.
Data is automatically transferred between these three registers according to the bus state; this
affects the states of internal flags, such as TDRE and RDRF.
After one frame of data has been transmitted or received by ICDRS, and the next datum is present
in the ICDRT in the transmission mode (i.e., when the TDRE flag is 0), that datum is transferred
automatically from ICDRT to ICDRS. After ICDRS has received or transmitted one frame of data
in the receive mode, a datum in ICDRS is automatically transferred to ICDRR when the previous
datum is not present in ICDRR (i.e., when the RDRF flag is 0).
When, excluding the acknowledge bit, there are fewer than 8 bits in one frame, the alignment of
the data for transmission and of received data varies according to the setting of the MLS bit in
ICMR. Data for transmission should span the selected number of bits from the MSB when MLS =
0. When MLS is 1, the data should span the selected number of bits from the LSB. Received data
is read from the LSB when MLS is 0 and from the MSB when MLS is 1.
ICDR is assigned to the same address as SARX; it is only accessible when the ICE bit of ICCR is
set to 1.
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