SH7144 Datasheet, PDF (312/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Initial Output in Complementary PWM Mode: In complementary PWM mode, the initial
output is determined by the setting of bits OLSN and OLSP in the timer output control register
(TOCR).
This initial output is the PWM pulse non-active level, and is output from when complementary
PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in
the dead time register (TDDR). Figure 11.38 shows an example of the initial output in
complementary PWM mode.
An example of the waveform when the initial PWM duty value is smaller than the TDDR value is
shown in figure 11.39.
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT3, 4 value
TGR4_A
TCNT_3
TCNT_4
Positive phase
output
Negative phase
output
TDDR
Initial output
Dead time
Active level
Active level
Time
Complementary
PWM mode
(TMDR setting)
TCNT3, 4 count start
(TSTR setting)
Figure 11.38 Example of Initial Output in Complementary PWM Mode (1)
Rev. 2.0, 09/02, page 272 of 732