SH7144 Datasheet, PDF (459/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W Description
6
WAIT
0
R/W Wait-insertion bit
This bit determines whether or not, in the I²C bus
format in the master mode, the interface waits after
the data other than the acknowledge bit has been
transferred. When WAIT = 1 is set, the IRIC flag in
ICCR is set to 1 after the final bit of the data has
become low, and the interface enters the wait state
(SCL is low). Clearing the IRIC flag in ICCR to 0
cancels the wait state. The acknowledge bit is t(en
transferred. When WAIT is set to 0, no wait state is
inserted and the data and acknowledge bits are
continuously transferred. The IRIC flag in ICCR is
set to 1, regardless of the setting of the WAIT bit,
when the transfer of the acknowledge bit has been
completed.
In slave mode, this bit is disabled.
0: Data and acknowledge bits are continuously
transferred.
1: A wait state is inserted between transfer of the
data bits and of the acknowledge bit.
5
CKS2
0
4
CKS1
0
3
CKS0
0
R/W Transfer clock select 2 to 0
R/W _{The CKS2 to CKS0 bits, together with the IICX0 bit}
R/W _{in SCRX, select the frequency of the transfer clock.}
This is used in the master mode. Set these bits to
obtain the required rate of transfer.
2
BC2
0
1
BC1
0
0
BC0
0
R/W Bit counter
R/W _{The BC2 to BC0 bits specify the number of bits to}
R/W _{be transferred in the next transfer. In transfer in the}
I²C bus format (when the SAR FS bit or the SARX
FSX bit is 0), the data bits plus one acknowledge bit
are transferred. Set the BC2 to BC0 bits in the
intervals between the transfer of frames. Do not set
the BC2 to BC0 bits to 000 unless SCL is low.
The bit counter is initialized to 000 on a reset or on
detection of the start condition. In addition, this
counter returns to 000 on completion of the transfer
of all data bits and the acknowledge bit.
Rev. 2.0, 09/02, page 419 of 732