SH7144 Datasheet, PDF (635/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Section 20 Mask ROM
This LSI is available with 256 kbytes of on-chip mask ROM. The on-chip ROM is connected to
the CPU, direct memory access controller (DMAC), and data transfer controller (DTC) through a
32-bit data bus (figure 20.1). The CPU, DMAC, and DTC can access the on-chip ROM in 8, 16
and 32-bit widths. Data in the on-chip ROM can always be accessed in one cycle.
Internal data bus (32 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0003FFFC
H'0003FFFD
H'0003FFFE
H'0003FFFF
Figure 20.1 Mask ROM Block Diagram
The operating mode, determines whether the on-chip ROM is valid or not. The operating mode is
selected using mode-setting pins FWP and MD3-MD0 as shown in table 3.1. If you are using the
on-chip ROM, select mode 2 or mode 3; if you are not, select mode 0 or 1. The on-chip ROM is
allocated to addresses H'00000000 to H'0003FFFF of memory area 0.
20.1 Usage Note
• Module Standby Mode Setting
Access to the on-chip ROM can be enabled/disabled by the module standby control register
(MSTCR1). The initial value enables the on-chip ROM operation. On-chip ROM access is
disabled by setting the module standby mode. For details, see section 24, Power-Down Modes.
Rev. 2.0, 09/02, page 595 of 732