SH7144 Datasheet, PDF (666/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

24.2.3 Module Standby Control Register 1 and 2 (MSTCR1 and MSTCR2)
MSTCR, comprising two 16-bit readable/writable registers, performs module standby mode
control. Setting a bit to 1, the corresponding module enters module standby mode, while clearing
the bit to 0 clears the module standby mode.
MSTCR1
Bit
Bit Name Initial Value R/W
15 to 12 —
All 1
R
11
MSTP27 0
R/W
10
MSTP26 0
R/W
9
MSTP25 0
R/W
8
MSTP24 0
R/W
7, 6 —
All 0
R
5
MSTP21 1
R/W
4
—
1
R
3
MSTP19 1
R/W
2
MSTP18 1
R/W
1
MSTP17 1
R/W
0
MSTP16 1
R/W
Description
Reserved
These bits are always read as 1, and should always
be written with 1.
On-chip RAM
On-chip ROM
Data transfer controller (DTC)
Direct Memory Access Controller (DMAC)
Set the identical value to MSTP25 and MSTP24,
respectively. When setting module standby, write
b'11, while clearing, write b'00.
Reserved
These bits are always read as 0, and should always
be written with 0.
I²C bus interface (IIC)
Reserved
These bits are always read as 1, and should always
be written with 1.
Serial communication interface 3 (SCI_3)
Serial communication interface 2 (SCI_2)
Serial communication interface 1 (SCI_1)
Serial communication interface 0 (SCI_0)
Rev. 2.0, 09/02, page 626 of 732