SH7144 Datasheet, PDF (407/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W Description
1
CKS1
0
R/W Clock Select 1 and 0
0
CKS0
0
R/W These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/8 clock (n = 1)
10: Pφ/32 clock (n = 2)
11: Pφ/128 clock (n = 3)
For the relation between the setting of CKS1 and
CKS2 and the baud rate, see section 13.3.9, Bit Rate
Register (BRR). n is the decimal display of the value
of n in BRR (see section 13.3.9, Bit Rate Register
(BRR)).
13.3.6 Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 13.7, Interrupt Sources.
Bit Bit Name Initial Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
6
RIE
0
R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
5
TE
0
R/W Transmit Enable
When this bit s set to 1, transmission is enabled.
4
RE
0
R/W Receive Enable
When this bit is set to 1, reception is enabled.
3
MPIE
0
R/W Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, refer to
section 13.5, Multiprocessor Communication
Function.
Rev. 2.0, 09/02, page 367 of 732