SH7144 Datasheet, PDF (472/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit
Initial
Bit Name Value R/W
Description
2 AAS 0
R/(W)* Slave-address detection flag
When the first frame after the start condition matches the
SVA6 to SVA0 bits of SAR or when the general-call address
(H’00) is detected in the I²C bus interface in the slave-
reception mode, the AAS flag is set to 1.
To clear the AAS flag, read a 1 from and then write a 0 to it.
When ICDR is written to (during transmission) or read from
(during reception), the flag is automatically reset.
0: Neither this device’s slave address nor the general call
address has been detected.
[Clearing conditions]
(1) Writing of data to ICDR (during transmission) or reading of
data from ICDR (during reception)
(2) Writing of 0 to this bit after reading it as 1
(3) Entering the master mode
1: The device’s slave address or the general call address has
been detected.
[Setting condition]
Detection of the slave address or general call address while in
the slave-receive mode and FS = 0.
1 ADZ 0
R/(W)*
General call address detection flag
In the I²C bus format in the slave-reception mode, the ADZ flag
is set to 1 when the general-call address (H'00) is detected in
the first frame after the start condition.
To clear the ADZ flag, read a 1 from and then write a 0 to it.
This flag is automatically reset when ICDR is written to (during
transmission) or read from (during reception).
0: The general call address has not been detected.
[Clearing conditions]
(1) Writing of data to ICDR (during transmission) or reading of
data from ICDR (during reception).
(2) Writing a 0 to this bit after reading it as 1
(3) Entering the master mode
1: The general call address has been detected.
[Setting condition]
Detection of the general call address in the slave-receive
mode (FSX = 0 or FS = 0).
Rev. 2.0, 09/02, page 432 of 732