SH7144 Datasheet, PDF (140/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Break on CPU Data Access Cycle
1. Register settings: UBARH = H'0012
UBARL = H'3456
UBBR = H'006A
UBCR = H'0000
Conditions set: Address: H'00123456
Bus cycle: CPU, data access, write, word
Interrupt requests enabled
A user break interrupt occurs when word data is written into address H'00123456.
2. Register settings: UBARH = H'00A8
UBARL = H'0391
UBBR = H'0066
UBCR = H'0000
Conditions set: Address: H'00A80391
Bus cycle: CPU, data access, read, word
Interrupt requests enabled
A user break interrupt does not occur because the word access was performed on an even
address.
Break on DMAC/DTC Cycle
1. Register settings: UBARH = H'0076
UBARL = H'BCDC
UBBR = H'00A7
UBCR = H'0000
Conditions set:
Address: H'0076BCDC
Bus cycle: DMAC/DTC, data access, read, longword
Interrupt requests enabled
A user break interrupt occurs when longword data is read from address H'0076BCDC.
2. Register settings: UBARH = H'0023
UBARL = H'45C8
UBBR = H'0094
UBCR = H'0000
Conditions set:
Address: H'002345C8
Bus cycle: DMAC/DTC, instruction fetch, read
(operand size is not included in conditions)
Interrupt requests enabled
A user break interrupt does not occur because no instruction fetch is performed in the
DMAC/DTC cycle.
Rev. 2.0, 09/02, page 100 of 732