SH7144 Datasheet, PDF (197/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W
6 DS
0
(R/W)*²
5 TM
0
R/W
4 TS1
0
R/W
3 TS0
0
R/W
2 IE
0
R/W
Description
DREQ Select
Sets the sampling method for the DREQ pin in
external request mode to either low-level detection
or falling-edge detection. This bit is valid only with
CHCR_0 and CHCR_1. For CHCR_2 and
CHCR_3, this bit is always read as 0 and should
always be written with 0.
Even with channels 0 and 1, when specifying an on-
chip peripheral module or auto-request as the
transfer request source, this bit setting is ignored.
The sampling method is fixed at falling-edge
detection in cases other than auto-request.
0: Low-level detection
1: Falling-edge detection
Transfer Mode
Specifies the bus mode for data transfer.
0: Cycle steal mode
1: Burst mode
Transfer Size 1, 0
Specify size of data for transfer.
00: Specifies byte size (8 bits)
01: Specifies word size (16 bits)
10: Specifies longword size (32 bits)
11: Prohibited
Interrupt Enable
When this bit is set to 1, interrupt requests are
generated after the number of data transfers
specified in the DMATCR (when TE = 1).
0: Interrupt request not generated after DMATCR-
specified transfer count
1: Interrupt request enabled on completion of
DMATCR specified number of transfers
Rev. 2.0, 09/02, page 157 of 732