SH7144 Datasheet, PDF (304/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Example of Complementary PWM Mode Setting Procedure: An example of the
complementary PWM mode setting procedure is shown in figure 11.33.
Complementary PWM mode
Stop count operation
[1]
Counter clock, counter clear
source selection
[2]
[1] Clear bits CST3 and CST4 in the timer start register
(TSTR) to 0, and halt timer counter (TCNT) operation.
Perform complementary PWM mode setting when
TCNT_3 and TCNT_4 are stopped.
[2] Set the same counter clock and clock edge for channels
3 and 4 with bits TPSC2-TPSC0 and bits CKEG1 and
CKEG0 in the timer control register (TCR). Use bits
CCLR2-CCLR0 to set synchronous clearing only when
restarting by a synchronous clear from another channel
during complementary PWM mode operation.
Brushless DC motor control
setting
[3]
TCNT setting
[4]
[3] When performing brushless DC motor control, set bit BDC
in the timer gate control register (TGCR) and set the
feedback signal input source and output chopping or gate
signal direct output.
[4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000.
Inter-channel synchronization
setting
[5]
TGR setting
[6]
Dead time, carrier cycle
setting
[7]
[5] Set only when restarting by a synchronous clear from
another channel during complementary PWM mode
operation. In this case, synchronize the channel generating
the synchronous clear with channels 3 and 4 using the timer
synchro register (TSYR).
[6] Set the output PWM duty in the duty registers (TGRB_3,
TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4,
TGRD_4). Set the same initial value in each corresponding
TGR.
PWM cycle output enabling,
PWM output level setting
[8]
[7] Set the dead time in the dead time register (TDDR), 1/2 the
carrier cycle in the carrier cycle data register (TCDR) and
carrier cycle buffer register (TCBR), and 1/2 the carrier cycle
plus the dead time in TGRA_3 and TGRC_3.
Complementary PWM mode
setting
[9]
[8] Select enabling/disabling of toggle output synchronized with
the PWM cycle using bit PSYE in the timer output control
register (TOCR), and set the PWM output level with bits OLSP
Enable waveform output [10]
and OLSN.
PFC setting
[9] Select complementary PWM mode in timer mode register 3
(TMDR_3). Do not set in TMDR_4.
[11]
[10] Set enabling/disabling of PWM waveform output pin output in
the timer output master enable register (TOER).
Start count operation
[12] ^{[11] Set the port control register and the port I/O register.}
[12] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start
the count operation.
<Complementary PWM mode>
Figure 11.33 Example of Complementary PWM Mode Setting Procedure
Rev. 2.0, 09/02, page 264 of 732