SH7144 Datasheet, PDF (222/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

CK
DRAK
Bus
cycle
DACK
CPU
CPU
CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W)
Figure 10.22 Burst Mode, Dual Address and Edge Detection
CK
DRAK
Bus
cycle
DACK
CPU
CPU
CPU Dummy
DMAC
DMAC
DMAC
Figure 10.23 Burst Mode, Single Address and Edge Detection
DMAC
10.4.6 Source Address Reload Function
Channel 2 has a source address reload function. This returns to the first value set in the source
address register (SAR_2) every four transfers by setting the RO bit of CHCR_2 to 1. Figure 10.24
illustrates this operation. Figure 10.25 is a timing chart for reload ON mode, with burst mode,
autorequest, 16-bit transfer data size, SAR_2 increment, and DAR_2 fixed mode.
DMAC
DMAC control block
Transfer
request
Reload control
4th count
RO bit = 1
CHCR_2
Count signal
DMATCR_2
Reload signal
Reload
signal
SAR_2
(initial value)
SAR_2
Figure 10.24 Source Address Reload Function
Rev. 2.0, 09/02, page 182 of 732