SH7144 Datasheet, PDF (32/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Figure 14.21 Scheme of Slave Transmit Operation .................................................................... 461
Figure 14.22 Scheme of TRS Bit Setting in Slave Mode ........................................................... 462
Section 15 A/D Converter
Figure 15.1 Block Diagram of A/D Converter (For One Module) ............................................. 464
Figure 15.2 A/D Conversion Timing .......................................................................................... 473
Figure 15.3 External Trigger Input Timing ................................................................................ 474
Figure 15.4 Definitions of A/D Conversion Accuracy ............................................................... 476
Figure 15.5 Definitions of A/D Conversion Accuracy ............................................................... 476
Figure 15.6 Example of Analog Input Circuit ............................................................................ 477
Figure 15.7 Example of Analog Input Protection Circuit ........................................................... 479
Section 16 Compare Match Timer (CMT)
Figure 16.1 CMT Block Diagram............................................................................................... 481
Figure 16.2 Counter Operation ................................................................................................... 484
Figure 16.3 Count Timing .......................................................................................................... 485
Figure 16.4 CMF Set Timing...................................................................................................... 486
Figure 16.5 Timing of CMF Clear by the CPU .......................................................................... 486
Figure 16.6 CMCNT Write and Compare Match Contention..................................................... 487
Figure 16.7 CMCNT Word Write and Increment Contention .................................................... 487
Figure 16.8 CMCNT Byte Write and Increment Contention...................................................... 488
Section 18 I/O Ports
Figure 18.1 Port A (SH7144)...................................................................................................... 553
Figure 18.2 Port A (SH7145)...................................................................................................... 554
Figure 18.3 Port B ...................................................................................................................... 557
Figure 18.4 Port C ...................................................................................................................... 559
Figure 18.5 Port D (SH7144)...................................................................................................... 561
Figure 18.6 Port D (SH7145)...................................................................................................... 562
Figure 18.7 Port E (SH7144) ...................................................................................................... 566
Figure 18.8 Port E (SH7145) ...................................................................................................... 567
Figure 18.9 Port F....................................................................................................................... 569
Section 19 Flash Memory (F-ZTAT Version)
Figure 19.1 Block Diagram of Flash Memory............................................................................ 572
Figure 19.2 Flash Memory State Transitions.............................................................................. 573
Figure 19.3 Boot Mode............................................................................................................... 574
Figure 19.4 User Program Mode ................................................................................................ 575
Figure 19.5 Flash Memory Block Configuration........................................................................ 576
Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode ........................ 584
Figure 19.7 Flowchart for Flash Memory Emulation in RAM ................................................... 585
Figure 19.8 Example of RAM Overlap Operation (RAM[2:0] = B'000).................................... 586
Figure 19.9 Program/Program-Verify Flowchart........................................................................ 588
Figure 19.10 Erase/Erase-Verify Flowchart ............................................................................... 590
Section 20 Mask ROM
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