SH7144 Datasheet, PDF(37/773 Page) Renesas Technology Corp – Hitachi SuperH RISC engine

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SH7144 Datasheet, PDF (37/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

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Table 11.17 TIORL_4 (channel 4)..............................................................................................212

Table 11.18 TIORH_0 (channel 0) .............................................................................................213

Table 11.19 TIORL_0 (channel 0)..............................................................................................214

Table 11.20 TIOR_1 (channel 1) ................................................................................................215

Table 11.21 TIOR_2 (channel 2) ................................................................................................216

Table 11.22 TIORH_3 (channel 3) .............................................................................................217

Table 11.23 TIORL_3 (channel 3)..............................................................................................218

Table 11.24 TIORH_4 (channel 4) .............................................................................................219

Table 11.25 TIORL_4 (channel 4)..............................................................................................220

Table 11.26 Output Level Select Function .................................................................................230

Table 11.27 Output Level Select Function .................................................................................231

Table 11.28 Output level Select Function...................................................................................233

Table 11.29 Register Combinations in Buffer Operation ...........................................................242

Table 11.30 Cascaded Combinations..........................................................................................245

Table 11.31 PWM Output Registers and Output Pins ................................................................248

Table 11.32 Phase Counting Mode Clock Input Pins .................................................................252

Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 1........................................253

Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 2........................................254

Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 3.........................................255

Table 11.36 Up/Down-Count Conditions in Phase Counting Mode 4........................................256

Table 11.37 Output Pins for Reset-Synchronized PWM Mode ..................................................258

Table 11.38 Register Settings for Reset-Synchronized PWM Mode..........................................258

Table 11.39 Output Pins for Complementary PWM Mode ........................................................261

Table 11.40 Register Settings for Complementary PWM Mode ................................................262

Table 11.41 Registers and Counters Requiring Initialization .....................................................268

Table 11.42 MTU Interrupts .......................................................................................................285

Table 11.43 Mode Transition Combinations ..............................................................................307

Table 11.44 Pin Configuration....................................................................................................340

Table 11.45 Pin Combinations....................................................................................................340

Section 12 Watchdog Timer

Table 12.1 Pin Configuration......................................................................................................350

Table 12.2 WDT Interrupt Source (in Interval Timer Mode) .....................................................357

Section 13 Serial Communication Interface (SCI)

Table 13.1 Pin Configuration......................................................................................................363

Table 13.2 Relationships between N Setting in BRR and Effective Bit Rate B0 ........................373

Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...............................374

Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...............................374

Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...............................375

Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4) ...............................375

Table 13.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator

(Asynchronous Mode) ..............................................................................................376

Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ....................377

Rev. 2.0, 09/02, page xxxv of xxxviii

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